The present invention relates generally to a method and apparatus for providing electrical contact between a semiconductor device under test (DUT) and a tester system during semiconductor device testing, and more particularly to a method and apparatus for electrically contacting a DUT to a tester system in a final test process.
After packaging, semiconductor devices undergo quality and performance checks and tests. The semiconductor device or semiconductor device under test (DUT) requires an electrical connection with a current source of a tester for performing the electrical conductivity, performance and connectivity tests. Systems and devices have been devised for placement and positioning of electrical and mechanical probes on desired test points of the DUT. Conventional designs often result in damage to the semiconductor leads of the DUT during testing. For example visual mechanical (VM) defects such as indentation marks, burr marks, bent leads and the like obtained during testing from conventional test devices may make an otherwise finished and faultless semiconductor device defective.
In some conventional designs contacting probes such as pogo pins having sharp tips are used. Sometimes the sharp pogo tips are off center such that the tip of the pogo pin does not contact the center top surface of the lead of the semiconductor DUT as intended. Defects such as burrs are incurred on the leads or balls of the semiconductor DUT, which may contribute to lead defects. This problem is amplified when the DUT is packaged with multiple leads having fine pitch and narrow lead width. In such devices the risk of misalignment of the sharp contacting probe tips with the lead of the DUT is high. Additionally, compression forces of the probe on the DUT may result in substrate cracks, package cracks, lead defects, ball defects and the like when the probe contacts the DUT. As a result, such conventional test devices and systems can contribute to semiconductor yield losses. Even if the semiconductor device meets test standards, the life span of the device and the pogo pins may be shortened as a result of the testing process.
Attempts have been made to design systems without sharp contacting probes and have incorporated liquid metal configurations. However, such conventional designs can contaminate the semiconductor DUT and may prevent additional processing of the semiconductor such as solder after test. Also, such systems are not suitable in batch test configurations or frequent connect/disconnect of the semiconductor DUT with the tester applications. Even in these designs and systems, there may still be high compression forces generated that contribute to semiconductor yield losses.
Therefore, there is a need for a method for electrically connecting and an electrical connection between a semiconductor DUT and a tester that overcomes or at least alleviates the problems associated with conventional connections between semiconductor DUTs and testers during final testing of semiconductor devices.